Programmable switches are used in a variety of ways in modern day integrated circuits. One example of the implementation of programmable switches includes their use in field programmable gate arrays (FPGAs). Typically, a field programmable gate array (FPGA) has an array of logic elements and wiring interconnections with thousands, or even tens of thousands, of programmable interconnects so that the FPGA can be configured by the user into an integrated circuit with defined functions. Each programmable interconnect, or switch, can connect two circuit nodes in the integrated circuit to make (or break) a wiring interconnection or to set the function or functions of a logic element.
Generally an antifuse, such as described in U.S. Pat. No. 5,324,681, which issued to Lowrey et al. on Jun. 28, 1994, is used as a programmable interconnect for the wiring and circuit elements of a FPGA. The antifuse integrally combines the functions of a switching element which makes the interconnection and a programming element which stores the state of the switching element, either "off" or "on." Thus an antifuse occupies little space on the integrated circuit, but has the disadvantage of not being reprogrammable. This single-time programmability makes the antifuse difficult to test and unsuitable for a large class of applications where reprogrammability is required.
Alternative programmable interconnects use a metal oxide semiconductor field programmable transistor (MOSFET) as the switching element. The MOSFET is controlled by the stored memory bit of a programming element. Most commonly, this programming element is a dynamic random access memory (DRAM) cell. Such DRAM based FPGAs are reprogrammable, but the programming of the switching elements is lost whenever power is turned off. A separate, non-volatile memory cell must be used to store the programmed pattern on power down, and the FPGA must be reprogrammed each time the device is powered back up.
With the increasing array density of successive generations of DRAM chips, the attractiveness of merging non-volatile memory functions onto the DRAM chip has increased. However, any successful merged technology product must be cost competitive with the existing alternative of combining separate chips at the card or package level, each being produced with independently optimized technologies. Any significant addition of process steps to an existing DRAM technology in order to combine such functions becomes rapidly cost prohibitive due to the added process complexity cost and decreased yield.
Device size and required programming voltages pose additional problems to merging non-volatile memory cells with DRAM memory cells. An example of a non-volatile memory cell is a MOSFET with a floating gate which may be charged and discharged. Charging and discharging the floating gate provides for the non-volatile programmability. A control gate forms a capacitive cell with the floating gate to retain charge on the floating gate in a "programmed" state. The plates of the capacitive cell must be fabricated with a large enough surface area to provide a capacitive coupling ratio which is sufficient to retain charge and is able to withstand the effects of parasitic capacitances vis a vis other circuit components. The shrinking device size in the increased cell density array found on DRAM chips necessitates increasing programming voltages in order to retain the required capacitance levels unless the size of the capacitive cell can be maintained. Increasing the programming voltage, however, increases the power dissipation and future generations of non-volatile memory cell devices will require lower power dissipation.
Modern DRAM technologies are driven by market forces and technology limitations to converge upon a high degree of commonality in basic cell structure. For the DRAM technology generations from 4 Mbit through 1 Gbit, the cell technology has converged into two basic structural alternatives; trench capacitor and stacked capacitor. A method for utilizing a trench DRAM capacitor technology to provide a compatible EEPROM cell has been described in U.S. Pat. No. 5,598,367. A different approach is needed for stacked capacitors however.
Another problem for the application of non-volatile memory cells in FPGAs relates to the ability of these cells to drive the MOSFET switching elements. Existing non-volatile memory cells do not have a sufficiently high voltage output. Sense amplifiers must be used to convert the small output signal from a non-volatile memory cell to a full voltage digital signal which is then used to load the DRAM cell.
One approach to solving this problem is described in U.S. Pat. No. 5,764,096, which issued to Lipp et al. on Jun. 9, 1998. U.S. Pat. No. 5,764,096 provides a general purpose non-volatile, reprogrammable switch, but does not achieve the same using the commonality in basic DRAM cell structure. Thus, the Lipp patent does not achieve the desired result of providing non-volatile memory functions on a DRAM chip with little or no modification of the DRAM optimized process flow.
Thus, there is a need for novel DRAM technology compatible non-volatile, reprogrammable switches for use in FPGAs and other applications. It is desirable that such DRAM technology compatible non-volatile, reprogrammable switches be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. It is further desirable that such DRAM technology compatible non-volatile, reprogrammable switches operate with lower programming voltages than that used by conventional EEPROM cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.